What kind of processor does the ps3 have

The most common Phat model console released and in Australia were 40, 60, 80 Gig The 60Gb was the only model released in Aus…. The US Air force cluster is being used for high-resolution image processing, pattern recognition, and other military use. Collectible card games. What software does PS3 use? What made the PS3 hard to develop for? What architecture does the PS3 use? What kind of firmware do I need for my PS3? How much did it cost to build a PS3 supercomputer? Which is an example of an industrial process?

What are the advantages of a PS3 supercomputer? What kind of processor does a PS3 have? In any case, many research papers made by IBM and other authors compiled more realistic speeds using practical experiments [9]. That is the part of the silicon that is in charge of commanding the rest.

Remember how I divided Cell into different areas before? Well, the same can be done with the PPE. We are going to take a look at the insides of the PPU just now. Last but not least, the use of a well-known architecture is good news for existing compilers and codebases which, for a new console, is a big starting advantage. This will become more evident when I show you the modularised execution units soon.

On the other side, some elements are missing from the original specification, such little-endian mode in fact, Cell only operates in big-endian and just a handful of opcodes. The capabilities of the PPU are defined by what each block can do and how:. The first block is called Instruction unit IU and as its name suggests, it pulls instructions from L2 cache and signals other units to perform the requested operation.

Like its i contemporaries , part of the instruction set is interpreted with the use of microcode the IU embeds a small ROM for this purpose. Instruction issuing is carried out with a stage pipeline , though in practice the total number of stages will greatly vary depending on the type of instruction.

For instance, the branch prediction block may bypass great parts. Now for the interesting parts, The IU is dual-issued : in some cases, the IU will dispatch up to two instructions at the same time, consequently improving throughput greatly. Behind the scenes, the IU is just alternating between the two threads at each cycle, giving the appearance of multi-threading.

In reality, there are 64 in total! Thus, the latter are single-threaded. All in all, combining dual-threading with dual-issuing, the PPU can execute up to four instructions per cycle. The following blocks grant the PPU the ability to execute load-store instructions and carry out memory management. As a consequence, this unit has direct access to memory and registers.

To make a long story short, the MMU handles memory addressing using a virtual address map combined with memory protection. It carries out integer arithmetic, such as division, multiplication, bit rotation similar to bit shifting but discarded bits are returned to the other end and count-leading zero useful for normalising vertex coordinates, for instance.

Its pipeline is stages long. Remember that wide main bus the EIB? IBM designed the PPE so engineers may combine it with other processors to accelerate particular applications i. To answer that, we need to take a look at how the memory blocks work and how they connect to Cell.

Rambus, like any other company, improves upon their inventions. XDR is connected to Cell using two bit buses, one on each pair.

Additionally, the MIC buffers memory transfers to improve bandwidth, but it has a big limitation: large byte alignment. But if the data is smaller than B or it requires alternating between writing and reading, performance penalties appear. That being said, is the MIC a bottleneck or an accelerator? Well, you have to put it into perspective, bandwidth optimisation is critical in data-hungry systems. The PS3 also enables games to use 2 GB from its internal hard drive as a working area similarly to what the original Xbox provided [15].

This is common practice with video console hardware, as general-purpose can perform a wide range of tasks, but are not specialised in anything. Videogame consoles require only a subset of skills physics, graphics and audio, for instance so co-processors bring them up to their task.

Cell includes eight of them , although one is disabled while the console boots up. This is because chip fabrication requires an exceptional amount of precision Cell initially used the 90nm fabrication process and the machinery is not perfect. Thus, if one of them comes out defective, the whole chip is not discarded.

Remember what I explained before about the adoption of elements from homogeneous computing? Well, these coprocessors are somewhat general-purpose and not restricted to a single application, so they will be able to assist in a wide range of tasks, that is, as long as developers can program them properly. As the front door to Cell, the SBI operates in two modes: bus master where the SPE is adapted to requests data from outside or bus slave where the SPE is set to receive orders from outside.

Instead, the SPU contains local memory used as working space. However, the contents of local memory can be moved back and forth using the MFC. Nonetheless, it performs exceptionally well at vector processing.

On the other side, to preserve memory, SPU instructions are much smaller, just 32 bits long. The first part contains the opcode and the rest can reference up to three operands to be computed in parallel.

This is very relatable to the previous Vector Floating Point Unit debuted in the PS2, but a lot has changed since then. On the other hand, the SPU will never dual-issue instructions that depend on each other, thus, mitigating data hazards that may emerge. Notice that there are only KB available to store the program. As we reach the end of Cell, you may ask how are developers supposed to program this monster? Well, similarly to the previous programming models devised for the Emotion Engine, IBM proposed the following methodologies [21] :.

There are three possible patterns:. Thus, codebases implementing SPE-centric algorithms may be harder to port to other platforms. As you can imagine, while the multi-core design of Cell accelerates emerging techniques such as procedural generation , none of these designs are particularly simple to implement, especially considering game studios prefer codebases that can be shared across different platforms.

To give you an example, the developers of the Unreal Engine 3 Epic Games demonstrated the limitations of the SPUs while trying to implement their collision detection system [22]. Xbox or i PCs, both of which provide advanced prediction techniques in all their cores. Hence, Epic Games had to resort to further optimisations only compatible with Cell.

If you thought that Cell, with all its quirks, could take care of every task of this console, then let me tell you something hysterical: Sony fitted a separate chip for 3D graphics. It appears that even with a supercomputer chip, Sony still had to fetch a GPU to finalise the Playstation 3. I will now perform the same level of analysis previously done with Cell, this time focusing on RSX and its graphics capabilities.

Though in subsequent years, the number of companies slowly reduced to the point that by , only Ati and Nvidia remained as the flagship video card suppliers in the PC market. In my previous Xbox analysis , I talked about the Geforce3 and their debuting pixel shaders, so what has changed since then? The memory bus runs at MHz with a theoretical bandwidth of up to That includes vertex data, shaders, textures and commands.

This comes in handy if the rendered frame will be post-processed by an SPU, for instance. That may be true in certain cases, but unless they mention these, that generic claim is, in my opinion, misguiding.

Its pipeline model is very similar to the Geforce3 , but super-charged with five years of technological progress. As with any other GPU, there must be a block of circuitry in charge of receiving the orders from outside. The host is responsible for reading commands from memory either at local or main and translating them into internal signals that other components in RSX understand, this is done with the use of four sub-blocks:.

As you can see, commands and data pass through many buffers and caches before reaching the final destination. This is intentional, as it prevents stalling the pipeline due to different units and buses operating at different speeds. Furthermore, the instruction limit has been increased to instructions originally, was the limit! Also, the VPE contains four texture samplers that pull texture colours during this stage, in case programmers want to use this unit to perform some operations on them.

The rasterizer accepts points, lines including strips and closed types , triangles including strips and fans , quadrilaterals and regular polygons. Naturally, as with this console generation, the rasterizer works with sub-pixel coordinates , where the sampling points are half-coordinates 0. This allows the unit to apply anti-aliasing methods such as Multisampling afterwards. Multisampling consists in rasterizing the same geometry multiple times but shifting a few sub-pixels apart at every batch the RSX supports four different shifting modes and then computes an average.

This results in a smoothed image. Furthermore, this unit also performs z-culling using dedicated RAM within the RSX it has a capacity of around three million pixels. This saves processing pixels and stencils that have already been rendered and allows to perform early z-test on incoming geometry. A separate unit is used for rasterizing 2D objects sprites , although this one is isolated from the 3D pipeline. Consequently, RSX works in two modes, 2D and 3D, but intermittently switching between them is expensive in terms of performance.

To organise multiple units working concurrently, another sub-block called Shader Quad Distributor SQD is placed to dispatch quads to each fragment unit. Afterwards, each fragment unit loads the fragment program. To compute operations, each pipe contains the enormous amount of bit registers. On top of all that, each pipe can process multiple quads in parallel multi-threading , though the number of quads processed in parallel depending on the number of registers allocated to the fragment program no.

In global terms, up to quads can be processed in parallel. The fragment units provide similar arithmetic-type instructions to the vertex unit, with the addition of texture-related opcodes, such as multiple types of texture fetching since textures can be encoded using many structures and then compressed and unpacking. All of this to ease programming and avoid learning low-level APIs from the ground up. Notice that main RAM cache is significantly larger, this was a conscientious decision made to compensate for higher latency.

There are two sets of ROPs made of four blocks each eight in total. Each group performs z-testing, alpha blending and the final write to memory. All in all, this circuitry can process up to 16 z-values and 8 pixel colours per clock. To save further bandwidth, ROPs also provide colour compression and z-compression. Thus, saving the GPU from doing page swaps used for memory addressing while transmitting the frame buffer for display, consequently improving bandwidth. Gone are the days of console-proprietary video sockets and dozens of analogue signals squashed together in a single socket to accommodate every region in the earth.

The Playstation 3 finally incorporated a unified video signal soon to be adopted worldwide: the High Definition Media Interface HDMI , used for transferring both audio and video at the same time.

The HDMI connector is made of 19 pins [33] , all in a single socket. To this day, the HDMI protocol is continuously being revised [34] , with new versions of the specification offering more features i. The last protocol compatible with the PS3 is version 1. Well, it so happens that the lifetime of this console overlapped with a short-lived fever for 3D tellies the so-called 3DTV [36]. In other words, there are no longer dedicated audio chips.

I presume this is because the capabilities have reached our cognitive limit That being said, where is the audio signal sent for broadcast? The RSX. This chip also contains the ports used to broadcast raw audio signals to the TV.

This is very similar to the architecture the original Xbox adopted back in the day. So, while it still remains an obscure piece of silicon, it does a superior job consolidating many interfaces and protocols, both external i. USB, Ethernet, etc and internal i. Furthermore, the southbridge implements encryption algorithms to protect the communication between standard protocols in a seamless way, such as the Hard Drive data. Thanks to wide the adoption of Bluetooth technology, wired controls are now a thing of the past.

This comes at the expense of the haptic feedback Rumble , however. A year later, Sony surprised players with the Dualshock 3 , which restored the haptic motor. Having mentioned the PS2 chips, I guess this is my cue to talk about backwards compatibility of the Playstation 3 once in for all. Circa when the PS3 was announced, the Cell was a radical departure from anything on the market.

The very first dual core processors in the world, the Athlon x2 and the Pentium D, were released in May , the same month that the PS3 was announced at E3. This allowed for a degree of flexibility when it came to, say, budgeting for a higher resolution texture. The SPEs Synergistic Processing Elements are what made Cell unique and, of course, what made it uniquely challenging for game developers to work with. The SPEs were a set of 8 further streamlined processor cores, with limitations such as not feature cache and not having branch prediction.

As a result, there was an emphasis on writing code optimized for high single-threaded performance. This was great if you were rocking a Core 2 Duo or an Xbox , with its 3 3. Oftentimes, developers simply opted to make minimal use of the SPEs, offloading most of the processing load to the single PPE.

One only needs to take a look at the visual jump from Uncharted 1 to The Last of Us. This was obviously problematic from a performance viewpoint. While multiplats generally fared poorly on PS3, first-party titles were another matter, offering better visual fidelity and scope than most exclusives on the Xbox A studio like Naughty Dog, with greater experience working with the harder and better accessibility to Sony itself were able to wring the most out of the SPEs over time.

Environmental effects look more detailed, higher resolution textures were now being accomodated anyone remembers this tree from Uncharted 2? In many ways, the optimization implemented during the later days of the PS3 CELL processor set the benchmark for future PS4 development framework and tools.